// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2006 by Lattice Semiconductor Corporation
// --------------------------------------------------------------------
//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Lattice Semiconductor Corporation
//                     5555 NE Moore Court
//                     Hillsboro, OR 97214
//                     U.S.A
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//                     TEL: 1-800-Lattice (USA and Canada)
//                          503-268-8001 (other locations)
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//                     web: http://www.latticesemi.com/
//                     email: techsupport@latticesemi.com
//
// --------------------------------------------------------------------
//
//  Project:           7:1 LVDS Video Interface
//  File:              LVDS_7_to_1_TX_sapphire.v
//  Title:             LVDS_7_to_1_TX_sapphire
//  Description:       Tx module of this reference design for Sapphire architecture
//
// --------------------------------------------------------------------
// Code Revision History :
// --------------------------------------------------------------------
// Ver: | Author   | Mod. Date  | Changes Made:
// V1.0 | shossner | 2010-04-25 | Initial Release
// V1.1 | shossner | 2010-11-03 | Accomodation for IPexpress module update
//
// --------------------------------------------------------------------

`timescale 1 ns/ 1 ps

module LVDS_7_to_1_TX_12Lane 
     (
      RST_Tx  ,
              
      OLED1_T0_in   ,
      OLED1_T1_in   ,
      OLED1_T2_in   ,
      OLED1_T3_in   ,
	  OLED2_T0_in   ,
      OLED2_T1_in   ,
      OLED2_T2_in   ,
      OLED2_T3_in   ,
      OLED2_T4_in   ,
      OLED2_T5_in   ,
      OLED2_T6_in   ,
      OLED2_T7_in   ,        
      eclk    ,
      clk_s   ,
      stop    ,
      sclk    ,
      TCLK_out1,
      TCLK_out2,
      TCLK_out3,	  
      OLED1_T0_out  ,
      OLED1_T1_out  ,
      OLED1_T2_out  ,
      OLED1_T3_out  ,
	  OLED2_T0_out  ,
      OLED2_T1_out  ,
      OLED2_T2_out  ,
      OLED2_T3_out  ,
	  OLED2_T4_out  ,
      OLED2_T5_out  ,
      OLED2_T6_out  ,
      OLED2_T7_out  
    );

   input        eclk;     // Tx module 3.5x clock 
   input        clk_s;    // slow clock for reset circuit
   input        stop;     // eclksync control signal 
   input        RST_Tx;   // Tx module reset
     
   input  [6:0]  OLED1_T0_in;    // 7-bit parallel data
   input  [6:0]  OLED1_T1_in;    // 7-bit parallel data
   input  [6:0]  OLED1_T2_in;    // 7-bit parallel data
   input  [6:0]  OLED1_T3_in;    // 7-bit parallel data
   input  [6:0]  OLED2_T0_in;    // 7-bit parallel data
   input  [6:0]  OLED2_T1_in;    // 7-bit parallel data
   input  [6:0]  OLED2_T2_in;    // 7-bit parallel data
   input  [6:0]  OLED2_T3_in;    // 7-bit parallel data
   input  [6:0]  OLED2_T4_in;    // 7-bit parallel data
   input  [6:0]  OLED2_T5_in;    // 7-bit parallel data
   input  [6:0]  OLED2_T6_in;    // 7-bit parallel data
   input  [6:0]  OLED2_T7_in;    // 7-bit parallel data
   output       sclk;
   output       TCLK_out1; // LVDS clock output pair 
   output       TCLK_out2; // LVDS clock output pair 
   output       TCLK_out3; // LVDS clock output pair 
   output       OLED1_T0_out;   // LVDS data output pair 0
   output       OLED1_T1_out;   // LVDS data output pair 1
   output       OLED1_T2_out;   // LVDS data output pair 2
   output       OLED1_T3_out;   // LVDS data output pair 3
   output       OLED2_T0_out;   // LVDS data output pair 0
   output       OLED2_T1_out;   // LVDS data output pair 1
   output       OLED2_T2_out;   // LVDS data output pair 2
   output       OLED2_T3_out;   // LVDS data output pair 3
   output       OLED2_T4_out;   // LVDS data output pair 0
   output       OLED2_T5_out;   // LVDS data output pair 1
   output       OLED2_T6_out;   // LVDS data output pair 2
   output       OLED2_T7_out;   // LVDS data output pair 3

   wire   [11:0] tx_do;    // 4 serialized output data streams
   wire         reset;

assign reset = RST_Tx || stop  /* synthesis syn_keep = 1 */;


//--------------------------------------------------------------------
//-- IPexpress GDDR_7:1 Tx module
//--------------------------------------------------------------------
        
    //ip_gddr71tx LVDS_71_Tx (
            //.clkout     (TCLK_out), 
            //.ready      (), 
            //.refclk     (eclk), 
            //.sclk       (), 
            //.start      (1'b1), 
            //.sync_clk   (eclk),
            //.sync_reset (reset), //stop),
            //.data0      (T0_in), 
            //.data1      (T1_in), 
            //.data2      (T2_in), 
            //.data3      (T3_in), 
            //.dout       (tx_do)
        //);
		
	//ip_gddr71tx LVDS_71_Tx_inst (
	//.clkout(TCLK_out ),
	//.ready( ),
	//.refclk(eclk ),
	//.sclk(sclk ),
	//.start(1'b1 ), 
    //.sync_clk(clk_s ),
	//.sync_reset(reset ),
	//.data0(T0_in ),
	//.data1(T1_in ),
	//.data2(T2_in ), 
    //.data3(T3_in ),
	//.dout(tx_do ));
	
	ip_gddr71tx_12lane ip_gddr71tx_12lane_inst(
	.clkout1(TCLK_out1 ),
	.clkout2(TCLK_out2 ),
	.clkout3(TCLK_out3),
	.ready( ), 
	.refclk(eclk ), 
	.sclk(sclk ), 
    .start(1'b1 ), 
	.sync_clk(clk_s ), 
	.sync_reset( reset), 
	.data0(OLED1_T0_in ), 
	.data1(OLED1_T1_in ), 
	.data2(OLED1_T2_in), 
	.data3(OLED1_T3_in ), 
	.data4(OLED2_T0_in ), 
	.data5(OLED2_T1_in ), 
    .data6(OLED2_T2_in ), 
	.data7(OLED2_T3_in ), 
	.data8(OLED2_T4_in ), 
	.data9(OLED2_T5_in ),    
	.data10(OLED2_T6_in ), 
	.data11(OLED2_T7_in ),  
	.dout(tx_do ));
    
//-----------------------------------
        

   assign OLED1_T0_out = tx_do[0];
   assign OLED1_T1_out = tx_do[1];
   assign OLED1_T2_out = tx_do[2];
   assign OLED1_T3_out = tx_do[3];
   assign OLED2_T0_out = tx_do[4];
   assign OLED2_T1_out = tx_do[5];
   assign OLED2_T2_out = tx_do[6];
   assign OLED2_T3_out = tx_do[7];
   assign OLED2_T4_out = tx_do[8];
   assign OLED2_T5_out = tx_do[9];
   assign OLED2_T6_out = tx_do[10];
   assign OLED2_T7_out = tx_do[11];


endmodule


